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Thermal vias in a DPAK pad is OK

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发表于 2012-12-29 00:00:00 | 显示全部楼层 |阅读模式
Hello,

Is it allright to put thermal vias in the DPAK drain pad so that i can transport heat away to  some copper on the opposite surface.?

I have heard somewhere that its wrong, but in truth, cant see why it should be a problem?
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发表于 2012-12-29 00:00:00 | 显示全部楼层
Cause You are heating up under the soldermask ink on opposite surface. 2 ways to easely aviod this is to "open" in soldermask on opposite site or fill the via hole, the last one is very well known and used, as qfn packages has same problem .

But in the end it depends on the mounting fabric/assembly house      
                                         
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 楼主| 发表于 2012-12-29 00:00:00 | 显示全部楼层
thamks... i thought the fact that there's soldermask on the bottom  thermal spreading copper is irrelevant, i mean, if  hot solder goes through the via, then it will just melt the soldermask ink, harmlessly?


.....also, why would solder want to "wick" down a via?.......solder only wicks towards  hotter surfaces than the surface its on........and the bottom surface would not be hotter,  surely?      
  
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发表于 2012-12-29 00:00:00 | 显示全部楼层
If it is for heat transfer, you don't want thermal vias at all. The thermal is to cut groove between the pads and the copper plane, leaving only 4 thin traces connecting it. This is to prevent good heat transfer from the pads to the plane. The whole thing about thermal on vias is to isolate the heat from the pads to travel to the copper plane. That is for soldering purpose. If you don't have a thermal, the heat from the soldering iron get dissipated out onto the plane, that makes it hard to solder. But for your case, you use the via to transfer heat, the last thing you want is to put thermal to block the heat transfer from the via to the copper plane.      
                                         
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发表于 2012-12-29 00:00:00 | 显示全部楼层
If soldering is done by stove, I guess thermal vias is not an issue.
The problem exists if you espect perform further maintenance, due to heat will be drawn more accentuated, reducing thermal gradient.


+++         
                                         
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发表于 2012-12-30 00:00:00 | 显示全部楼层
Yes it IS ok to put vias in your DPAK large drain pad, it is very common to do this, although they should not have any thermal relief (which is what I think Alan is referring to) and they should not have solder paste on them as it does wick down the via holes.

If a manufactured board, and plenty of them then they should really be "plugged", smaller hand assembled prototypes should be fine without plugging.

As well as that your solder paste pad shape should not really cover the same size as the pad as that outs too much solder on the pad and can lead to solder balling etc, most prefer to reduce it to about 70% by making a matrix of shapes on the solder paste layer, if you are having solder vias you can make an anulus ring of solder paste around them to prevent any solder going down the hole.

If this component is to be used once then you can add vias in the single job, if it is likely to be used a lot then it may be better to do this in the component, add the vias in the component in the library - but not as vias but as pads.

You have not said which PCB package you are using, if using CADSTAR here is a guide on how to do it.      
                                         
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发表于 2012-12-30 00:00:00 | 显示全部楼层
                                                           As well as that your solder paste pad shape should not really cover the same size as the pad as that outs too much solder on the pad and can lead to solder balling etc, most prefer to reduce it to about 70% by making a matrix of shapes on the solder paste layer, if you are having solder vias you can make an anulus ring of solder paste around them to prevent any solder going down the hole.                                          Solder will spread all over the open pad area, not caring much about the stencil structure. The linked Cadstar thermal via guideline is in contrast talking about solder resist annular rings to prevent solder wicking.

I have tried similar constructs some years ago and found that some PCB manufacturers apparently have difficulties to reproduce clean solder mask structures in this situation. I got solder resist residuals on the remaining pad area that has to be cleaned manually. Due to this uncertain results we decided not to further pursue this method.

For high performance PCB, we generally go for metallized plugging (via in pad), because the surcharge is pretty much compensated by the increase in wiring density. For simple PCBs, small (e.g. 0.3 mm finished diameter) open thermal vias with a small solder resist opening (slightly above drill diameter) on the bottom side has turned out applicable. Some assembly service providers mentioned a reservation, that chip scale package ICs (CSP, QFN) might be "pulled down" by solder wicking, causing shorts between the downside pads. Although I didn't yet observe this problem, the consideration sounds plausible. But the problem definitely doesn't apply to packages like DPAK, MSOP or QFP with thermal pad.           
                                         
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 楼主| 发表于 2012-12-30 00:00:00 | 显示全部楼层
     Exactly. I did that many times, I put solder mask on the whole patch so I can use a big iron to solder the transistor/whatever on to it.      
                                         
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 楼主| 发表于 2013-1-2 00:00:00 | 显示全部楼层
IPC-7093 and numerousIC manufacturers guidline on thesetype of devices.
As FvM mentioned plugged vias is the best option but not always available due to cost. Done loads of designs with these features where via plugging was not an option, controlling the stencil and location of solder pastes helps and you can achieve a IPC-610 class  3  assembly without via plugging.      
                                         
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 楼主| 发表于 2014-8-7 00:00:00 | 显示全部楼层
Reference the thoughts on the thermal vias in the power pad "pulling" the fet out of line, and resulting in shorting, do you think this is a danger if we put vias in the pad of the AON6284 FET (DFN5X6 package)

DFN5X6 FET PACKAGE (AON6284 FET) datasheet
http://www.aosmd.com/res/data_sheets/AON6284.pdf

Here is the land pattern for the DFN5X6 package:
http://www.aosmd.com/pdfs/package/DFN5x6%20EP2.pdf      
  
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发表于 2014-8-7 00:00:00 | 显示全部楼层
I don't expect soldering problems with this rather coarse SMT structures if you have 0.3 mm vias in the large pads.      
                                         
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 楼主| 发表于 2014-8-8 00:00:00 | 显示全部楼层
by "coarse" do you mean that putting vias in the pads is ok, but a little crude and unprofessional?      
  
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