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楼主: treez

Thermal vias in a DPAK pad is OK

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 楼主| 发表于 2014-8-8 00:00:00 | 显示全部楼层
I think the sense is clear if you just read the words carefully. I said "coarse structures", which means that  pad size and pad clearance is so large that you don't get easily solder shorts.

Open thermal vias are not generally a problem for professional designs.      
                                         
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发表于 2014-10-3 00:00:00 | 显示全部楼层
                                                           For simple PCBs, small (e.g. 0.3 mm finished diameter) open thermal vias with a small solder resist opening (slightly above drill diameter) on the bottom side has turned out applicable                                          ..thanks, but how does having solder resist on  the bottom side annulus help?
(presumably you mean the solder resist on the bottom side to just be an annulus sitting on  the bottom side metal annulus of the thermal via?)

The problem with having solder resist on the bottom side annulus of a thermal via, is that in Eagle Pro if you put solder resist there, then you also end up with solder resist on the top side annulus of the thermal via, and of course, this is disastrous, because the top side is in the thermal pad of the power semiconductor, and we don't want solder resist in the pad.....so how, in Eagle Pro, does one  get solder resist on only the bottom side annulus of the thermal via?

Also, when you say "0.3mm", do you infer that eg 0.4mm is too big a via drill hole and solder would wick away down it, causing an improper solder connection?           
  
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发表于 2014-10-3 00:00:00 | 显示全部楼层
Is it true that Eagle has no option to make user specific via padstacks with e.g. different solder mask opening on top and bottom side? If so, some manual work in the postprocess like manipulating apertures may be required.

But in case of thermal vias, there's no need for different mask pads, because the component mask pad overlays the via pad and keeps the topside free from soldermask, whatever the via mask pad looks like.

I believe that via diameters above 0.3 mm aren't good for thermal vias, you can refer to other application notes and should collect your own experience.

Below a drawing of an open thermal via from an Amkor application note.



      
                                         
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 楼主| 发表于 2014-10-4 00:00:00 | 显示全部楼层
You ought to have the IPC-7351 pads libraries if you want a proper job.

1st you must decide on reflow or wave solder for each part affected. Many are different.

This site has the library for each CAD tool for sale.
http://www.pcblibraries.com/download...%20Library.zip

The most common mistakes are design from nexperience that result in bad solder joints, EMI, thermal issues.  Electrical skills are not enough.         
                                         
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发表于 2014-10-4 00:00:00 | 显示全部楼层
I don't put vias in the D2PAK pads.   If I use vias for heat transfer on these type devices, I leave the pad "clean" to maximize the surface area that is in contact with and soldered to the device's tab.  You don't want solder voids from poorly wicked solder, blowby, misaligned parts, etc. reducing your surface area and lowering thermal conductivity.  I place vias around the outer edge of the pad, connected to the pad with VERY VERY short, wide copper traces to provide maximum distance/area for the dissipation of heat into another layer.  As other have pointed out - it can be done (putting vias in the pad), but in my experience with some assembly shops, some can handle it better than others, even if a patterned soldermask is applied around the vias.   And plugging vias does add some cost.

On parts like QFN, you really don't have much choice, but even there you should choose to not pack in too many vias and consider a patterned/cross hatch soldermask or use smaller diameter vias to avoid creating solder wicking issues (vias causing loss of solder between PCB pad and paddle on underside of the QFN part).
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